In the integrated circuit (IC) industry, trench isolation is now being used to replace conventional local oxidation of silicon (LOCOS) in order to form improved field isolation structures. However, the dielectric material used to fill isolation trenches formed within a substrate may be substantially eroded during post-trench processing whereby adverse parasitic MOSFET devices are formed adjacent the active areas of an integrated circuit (IC). FIGS. 1-5 illustrate the parasitic MOSFET formation which occurs in a conventional shallow trench isolation (STI) integrated circuit (IC) process.
FIG. 1 illustrates a semiconductor trench structure 10. In FIG. 1, a semiconductor substrate or semiconductor wafer 12 is provided. A pad oxide or thermal oxide layer 14 is formed over the substrate 12. A thicker silicon nitride layer 16 is deposited on top of the thin oxide layer 14. Conventional photolithographic processing is used to etch an opening 18 through the silicon nitride layer 16 and the oxide layer 14 to expose a portion of the substrate 12. This opening in the dielectric layers 14 and 16 is then extended into the substrate by a silicon etch to form a shallow trench region 18. After formation of the shallow trench region 18, a thermal oxidation process is utilized to form a thin oxide liner layer 17 on both the sidewalls and the bottom surface of the trench 18 in FIG. 1.
FIG. 2 illustrates that a trench fill layer 20a is conformally deposited within the trench 18 after formation of the liner 17. Layer 20a is typically formed by depositing an insulator such as an oxide formed using ozonated tetraethylorthosilicate (TEOS) and is formed of a thickness greater than the trench depth plus the thickness of the silicon nitride layer 16. FIG. 2 illustrates a dashed line 19 within the layer 20a. Line 19 indicates a level to which the layer 20a will be subsequently polished to form a proper trench fill plug region using the silicon nitride layer 16 as a polish stop layer.
FIG. 3 illustrates the structure of FIG. 2 after chemical mechanical polishing (CMP) planarization of layer 20a has occurred. The CMP process forms a trench plug region 20b from the layer 20a illustrated previously in FIG. 2. As indicated in FIG. 3, a top surface 19 of the plug region 20b is roughly analogous to the dashed line 19 in FIG. 2. After CMP is complete, the silicon nitride layer 16, which is used as a CMP stop, is then removed by a wet etch process. After removal of the silicon nitride layer 16, at least one active area, indicated as active area 24, is defined at top surface of the substrate 12 in FIG. 3. Electrical devices are subsequently formed within the active area 24 of the substrate and interconnected by overlying conductive layers, not shown, to form a functional IC.
FIG. 4 illustrates the adverse erosion of the trench fill plug 20b which occurs from subsequent processing of the active area 24. After formation of the trench plug 20b in FIG. 3, the active area 24 is exposed to many etch processing steps and cleaning steps which will eventually erode the dielectric plug material 20b as these additional steps occur. It is known in the art that TEOS layers will etch in oxide etch environments faster than thermally grown oxide layers. This faster etch rate of TEOS when compared to thermal oxide (e.g., gate oxides and most sacrificial oxides) will further exacerbate the erosion of the plug region 20b compared to other IC regions since the trench plug 20b is typically made of TEOS. FIG. 4 illustrates a plug region 20c which is the plug region 20b (see FIG. 3) after being substantially eroded by subsequent semiconductor processing that is needed to make active circuitry in the region 24. As illustrated in FIG. 4, erosion of the plug to result in an eroded plug 20c forms an exposed sidewall 26 of the active silicon surface area 24. This sidewall area 26 is exposed to subsequent active area processing (e.g., gate oxide and gate polysilicon formation) whereby unwanted parasitic sidewall devices (e.g., an unwanted sidewall parasitic MOSFET) are formed on the sidewall 26 of the active area 24.
FIG. 5 illustrates a three-dimensional cross-sectional perspective of the device of FIG. 4. FIG. 5 illustrates the top surface of the active area 24 of FIG. 4 as well as the parasitic sidewall 26 which is adversely formed by trench plug erosion. FIG. 5 illustrates that a MOSFET source region 28 and a MOSFET drain region 30 are formed within the active area by conventional ion implantation and thermal activation. These source and drain region 28 and 30 are separated by a channel region 32 within the active area 24. As is known in the art, a gate dielectric layer (not specifically shown in FIG. 5) is formed over the channel region 32 and a conductive gate electrode (not specifically shown in FIG. 5) is then formed overlying this gate oxide and overlying the channel region 32. The gate electrode is used to control a conductivity of the channel region 32 between the current electrode regions 28 and 30 in FIG. 5.
The fact that the resulting structure in FIG. 5 is not planar results in several problems. In gate formation, typically a blanket polysilicon layer is deposited and selectively etched to leave the gate electrodes in the desired locations. Thus, there is polysilicon over the trench isolation areas, such as 20c, which must be removed. The polysilicon present in and over the cavity adjacent to sidewall 26, is thicker than the polysilicon over the planar areas where the gates are to be established. Thus, when the polysilicon is etched it is completely removed in the areas adjacent to the gates before it is removed from the cavity adjacent to sidewall 26. To remove this polysilicon in this cavity requires substantial overetching which will slowly etch the gate oxide adjacent to the gates. If this overetch is applied too long it will etch through this gate oxide and pit the substrate such as substrate 12 adjacent to the gates. If this occurs, the transistor adjacent to this pit is likely to fail because of a reduction in the gate oxide integrity. If this overetch is not applied long enough, the polysilicon is not completely removed from the cavity which results in electrical shorts across the trench isolation. This is commonly called polysilicon stringers. Thus, there is a critical range of overetching which, if violated in either being too long or too short, will cause a serious problem. The critical range of overetching becomes smaller and smaller as the technology scales down, particularly as gate oxide thickness reduces.
Additionally, due to the erosion present in the trench plug region 20c, a parasitic MOSFET sidewall channel region 34 is present in the structure of FIG. 5 once the gate electrode is formed. Due to the fact that parasitic channel region 34 will be exposed to gate oxide formation and lie adjacent a portion of a subsequently formed gate electrode, the channel region 34 is a parasitic transistor channel region which is formed between the electrodes 28 and 30 in parallel to the desired channel region 32. Due to the fact that threshold (Vt) adjust implants, well region doping profiles, and other implanted regions are formed in the substrate, doping concentrations of dopant atoms in the substrate is not constant throughout the depth of a semiconductor substrate 12. Therefore, the threshold voltage of the vertical sidewall 34 may be substantially different from a threshold voltage of the top channel region 32 which will have a substantially constant dopant across its surface due to the fact that it in not directed into the depth of the substrate as is channel region 34. Typically, a doping concentration of the region 34 integrated over the vertical sidewall will be less or more than a doping concentration at the active area surface 32. Therefore, the parasitic channel region 34 is likely to typically "turn on" and form a conductive inversion region (i.e., an unwanted parasitic leakage path) between the regions 28 and 30 before the actual transistor channel region 32 is "turned-on" creating undesirable MOSFET behavior. If the sidewall of the channel region 34 of FIG. 5 is deep, the likelihood of forming adverse polysilicon stringers when patterning polysilicon gate electrodes also increases. Therefore, this parasitic channel region 34 is disadvantageous altogether.
One way to reduce the adverse erosion of the trench region 20c as illustrated in FIG. 5 is to expose the trench region 20c to fewer etch environments. The prior art has attempted to reduce the amount of wet etching and reactive ion etching (RIE) of the trench fill material 20c by reducing the amount of processing in the active area 24. However, for each etch and/or clean process removed from the overall semiconductor flow, the active area 24 is not being fully or adequately processed in accordance with general IC processing standards. As a result, integrated circuit (IC) yield in the active area and/or IC performance may be adversely impacted due to reduced cleaning processing and reduced etch processing.
Another solution attempted in the prior art is to form the liner 17 of FIG. 1 from a silicon nitride layer or a silicon oxynitride layer. This silicon nitride liner 17 will not etch substantially in oxide/TEOS etch environments and will not etch substantially in substrate cleaning processes. Therefore, through use of this nitrided liner, the sidewall erosion of the trench fill material 20c should be reduced by the sidewall presence of silicon nitride or oxynitride 17. However, silicon nitride (in contact with a Si substrate) has been shown to cause stress induced defects near the active area which adversely impacts MOSFET devices. Furthermore, any deposition of additional material within the trench may change the aspect ratio of the trench opening 18 thereby adversely affecting subsequent deposition processing and trench filling.
In addition, the presence of both exposed oxide surfaces and exposed nitride surfaces when forming the trench layer 20a in FIG. 2 adversely affects the conformality and selectivity of the TEOS deposition process of FIG. 2. Also, silicon nitride and some nitrided oxides has a greater permitivity (.di-elect cons.) or dielectric constant whereby the capacitive coupling to the parasitic sidewall region 34 may actually be increased by using a nitrided film thereby exacerbating the problems discussed herein. Nitride layers also reduce subsequent oxidation of any exposed sidewall wherein it may be impossible to advantageously thicken a parasitic gate dielectric laterally adjacent an exposed sidewall channel region 34 via thermal oxide growth or the like. Therefore, the increased complexity and risk from using a nitride or nitrided trench fill liner is not always advantageous.
In another embodiment, polysilicon may be deposited within the trench 18 formed in FIG. 1 whereby this polysilicon can be thermally oxidized to form a polysilicon-oxide liner 17 in the hope of reducing sidewall erosion of the region 20c. Note that polysilicon-oxide is similar to thermal oxide in that it etches slower than TEOS which could reduce overall trench erosion over time. However, this process adds at least one other process step to the process flow (e.g., it adds at least the additional step of the deposition of the polysilicon), and may decrease a lateral dimension of the trench whereby filling of the trench via subsequent dielectric deposition processing is more complicated.
Therefore, a need exists in the industry for a trench fill process which reduces trench plug erosion of the plug 20c thereby eliminating or reducing the adverse device affects of the parasitic sidewall, poly stringers, and pitting the substrate without significantly complicating the process flow.